1/9 march 2001 AN1266 application note benchmarking flash nor and flash nand memories for code and data storage contents n introduction n cell structure n cell dimensions n multi level cells n operational differences n cost trends n conclusion n references introductiom when choosing a flash memory for a particular application it is important to know which type of flash memory is most suitable. there are now many manufacturers offering a wide range of flash memories and users can be daunted by the prospect of selecting the correct product for their application. this document aims to give a background on the underlying technologies associated with flash memories. it will give the reader a clearer picture of which type of flash memory to choose for their application. the advantages and disadvantag- es of each type of memory is discussed along with the under- lying principles that govern the properties of the memory. there are two fundamental array architecture that distinguish the type of the flash memory, nor and nand. although both these types of memories can store large amounts of data, only the nor type is suitable for fast random access required for ex- ecuting code directly from the flash memory, saving on shad- ow ram costs. cell structure the basic cell in a flash memory is a single mos transistor built with a floating gate between the control gate and the p- substrate. figure 1 shows a typical cross section of the transis- tor. figure 1. cross section of the basic flash memory cell ai03431 n + n + p sd c floating gate source control gate drain sd c
AN1266 - application note 2/9 the floating gate stores charge (electrons); the amount of charge on the gate determines whether the flash memory cell holds a value of 1 or 0. (in multi-bit cells more than one bit can be stored, this is discussed later). to read the contents of the cell a voltage is placed across cs; the current through ds depends on the charge stored in the floating gate. by measuring i ds the charge in the floating gate is found. there are various methods of laying out all of the floating gate transistors and connecting c, d and s in a flash memory array. figure 2 shows the connection technique for nor and nand flash memories. figure 2. cell connection techniques for nor and nand flash memories in the nor architecture a read is performed by connecting the source line to ground, raising the voltage level on the word line to the sense voltage and connecting the bit line to the sense amplifier. if the ad- dressed cell is programmed then no current flows through the bit line to the sense amplifier. 8, 16, 32 or more bits are read in parallel depending on the data bus width of the memory. programming a 0 to the cell is performed by simultaneously pulsing the bit line with 5v and the word line with 10v; the program/ erase controller may have to apply several pulses to program the cell to the correct level. all the cells in a block are erased at the same time; to erase a positive voltage (5v) is put on the source line and a neg- ative voltage (-8v) is pulsed on the word line; again several pulses may be required to erase all the cells correctly. figure 3. program/erase operations in nor architecture flash memories ai03432 bit line source line word line (a) nor flash array architecture bit line select bit line source word line (b) nand flash array architecture ground line select bit line source bit line ai03443 sd floating gate control gate 0v 5v 10v hot electron injection gnd (a) nor program sd floating gate control gate 5v floating C8v fowler- nordheim tunnelling (b) nor erase
3/9 AN1266 - application note in the nand architecture a read is performed by connecting the source line to ground, raising the voltage level on the word line to the sense voltage, turning on the correct group of cells using the bit line select and connecting the bit line to the sense amplifier. the word lines of all the other cells in the group are left set to ensure that the cells are in their on state; only the current in the selected state governs the current in the bit line, enabling that cells contents to be read. reading a current through a series of sev- eral cells and select transistors is a slow operation; the random access time is typically 25 m s. to program individual cells the word line is driven to a very high voltage (15 to 20v) and the bit line is connected to ground (0v); the unselected cells have to pass the programming current without being affected them- selves. to erase a sector the word lines of the sector are driven to ground (0v) and the p-well of the sec- tor is driven to a very high voltage (15 to 20v). figure 4. program/erase operations in nand architecture flash memories the higher voltage required in the nand architecture makes the voltage pumps in the silicon more difficult to design. the management, distribution and switching of these higher voltages is also more difficult. with 0.25 m technology this has not been a limiting factor, but as the technology shrinks the electric fields inside the silicon increase, making it more and more difficult to route the signals through nand devices. although the flash array is smaller in nand, the voltage pumps and associated electronics are larger. cell dimensions when the array is laid out on the silicon wafer there are limitations to the size that each cell can be squashed into. here the nand architecture has an advantage over nor. figure 5 shows typical layouts for nor and nand flash memories. ai03444 sd floating gate control gate float gnd 15-20v fowler- nordheim tunneling gnd (a) nand program sd floating gate control gate float float 0v fowler- nordheim tunneling (b) nand erase 18-20v
AN1266 - application note 4/9 figure 5. typical layouts of nor and nand flash memories the silicon area required for the basic cell in the nor configuration is 10f 2 (where f is the feature size, related to the technology used e.g. 0.18 m , 0.15 m etc.); the cell size is limited by the contact to gate dis- tance. the nand has a smaller configuration, requiring only 6f 2 , thereby allowing a greater theoretical density of cells for a given technology. however, the decoder area for nand configurations is much larger than that in nor configurations, as are the charge pumps; when considering the density as number of cells to the overall flash memory size, the difference between the two types of configuration is not clear cut in favor of nand (see reference [1]). multi-bit cells the basic cell in a flash memory can hold different charge levels (quantized only by the charge on a sin- gle electron), giving rise to the possibility of storing more than one bit of information in each basic cell. figure 6 shows the charge level possibilities for a traditional, previous generation flash memory and the levels for a 2-bit per cell multi-bit flash memory. the amount of charge stored determines i ds when the cell is read. figure 6. floating gate charge levels and output states ai03433 word line source line bit line basic cell bit line contact floating gate (a) nor layout bit line select word line ground line select source basic cell floating gate bit line (b) nand layout bit line contact ai03442 '1' state '0' state '11' state '00' state '01' state '10' state previous generation flash multi-bit flash
5/9 AN1266 - application note nor architectures have an advantage over nand in multi-bit cell flash memories and are likely to achieve a higher number of bits per cell compared to nand in the long term. in the nor architecture the sense amplifiers have direct access the each cell. in the nand architecture the sense amplifiers signal is read through several other cells; the charge stored in the read-through cells makes small, but signifi- cant differences to the value read, decreasing the accuracy. this makes it likely that four bits per cell can- not be achieved in nand architectures. four bits per cell will allow nor technology to make up the economic difference (in $/mbyte) lost due to the large cell size. nand parts with 2-bits per cell are being designed for release towards the end of the year 2000. nor parts with 2-bits per cell are already being shipped and 4-bits per cell are planned for late in 2001. figure 7. nor/nand equivalent cell size considering multi-bit cell technology operational differences there are differences in the way that nor and nand memories behave at a system level. table 1 at the end of this section summarizes the operational differences. block, sector and page architecture flash memories cannot erase one byte at a time. it is necessary to divide the memory into blocks (or sec- tors) of cells that can be erased together. if there is some information stored in the block when the block needs to be erased, it must be moved to another block prior to erasing, otherwise it will be lost. nor mem- ories offer block sizes between 16 kbytes and 128 kbytes. nand memories offer sector sizes between 8 kbytes and 16 kbytes. (the meaning of the word block and sector is the same, different suppliers use different terminology). the page concept is different for nor and nand memories. nor memories with page-mode group up to four addresses in the same page; these four addresses take longer for the first access compared to the subsequent accesses within the same page, often it is referred to as page-mode. in nand memories each sector is sub-divided into pages, usually about 512 bytes long. the read access time inside the page is fast, whereas jumping to another page is slow. each page should be programmed as a whole too. read access nor flash memories offer random access. parts with access times down to 35ns are available. page- mode memories are available that offer 150ns access for the first page access and 20ns for the subse- quent accesses in the page. burst interfaces allowing bus speeds up to 66mhz allow nor memories to be interfaced to a variety of burst mode microprocessors. 0.4 0.35 0.25 0.18 0.15 0.13 0.01 0.1 1 10 equivalent cell area ( m m 2 ) technology ( m m) 1-bit/cell nor 1-bit/cell nand 2-bit/cell nand 4-bit/cell nor ai03445
AN1266 - application note 6/9 nand flash memories offer fast access times for sequential reads from within the same page in the mem- ory. the first access to memory in the page typically takes 25 m s, with subsequent accesses taking typically 50ns until the end of the page is reached. programming nor flash memories can be programmed in random order, with each program operation taking approx- imately 10 m s per byte or word. multi-bit cell memories take longer to program, but include a program buff- er that allows parallel programming of many bytes or words, keeping the program rate per word at about 10 m s. in the future multi-bit cell nor flash memories will include larger program buffers to reduce the burden on the cpu and decrease the programming time per byte to less than 2 m s. nand flash memories program one page at a time; single byte programming is not possible. a page pro- grams in approximately 200 m s and is usually about 512 (or 528) bytes long. the programming rate is about 0.5 m s per byte. multi-bit cell nand flash memories take longer to program, approximately 900 m s per page or 2 m s per byte. erase nor flash memories have block sizes between 16 kbytes and 128 kbytes. typically a 64 kbyte block takes about 0.7s to erase. the long erase time is due to the need to program each cell in the block to 0 before erasing the cells; this operation is required to guarantee that the charge in all the floating gates is the same before the erase operation begins. in modern flash memories the program/erase controller manages this process automatically so that the microprocessor can perform other tasks during the erase cycle. nand flash memories typically have block sizes of 16 kbytes; these take about 2ms to erase. nand flash memories do not need to preprogram all their floating gates to the same level prior to erasing. valid blocks in nor flash memories 100% of the array is guaranteed to work for a full 100,000 program/erase cycles. after 100,000 cycles the probability of a cell failing is still very small. the benefits of having an array that is 100% guaranteed is: n storage algorithms do not need to store information on bad blocks, saving space and algorithm development. n code can be executed directly from the memory, either for boot purposes (for example in pc systems where the bios is in flash, then is shadowed in ram) or for both boot and application execution (for example in pdas where cost and power savings are achieved by executing directly from the flash and the amount of ram required is reduced). in nand flash memories not all of the blocks are guaranteed to work. typically 98% or more of the flash memory is guaranteed. furthermore it is possible for blocks to fail in service, these too need to be marked as bad. nand flash memories offer 250,000 program/erase cycles, but these are not guaranteed in the same way as nor flash.
7/9 AN1266 - application note table 1. operational difference summary cost trends until 4-bit per cell nor flash memory becomes available the basic cost of 2-bit per cell nand memories is slightly less than that of 2-bit per cell nor. figure 8 compares the cost trends for the 2-bit per cell ar- chitectures, also shown is the predicted cost of 4-bit per cell nor technology. at a system level the cost difference between nor and nand is not as wide as the graph suggests. many applications that make use of nand devices require additional controller chips, whereas there are nor flash memories that are compatible with most microprocessor buses. flash memory has become more common than eprom for boot devices; only nor flash memory offers boot capability. furthermore the same flash part can be used for application storage and execution. many systems require only one flash memory for boot code, application code and user data, vastly reducing system costs. figure 8. cost trends for multi-bit cell flash memories operation nor nand summary random read 35 to 150ns 25 m s nor C true random access. nand C slow page selection time. sequential read 20 to 150ns 50ns nor C true random access. nand C page read from buffer. program time 5 m s/byte random 0.5 m s/byte sequential only nor C true random programming. nand C page or sequential partial page programming. erase time 0.7 s/128 kbyte 2 ms/16 kbyte nor C internally the flash has to program all cells first. nand C quick erase operations. array good 100% 98% nor C all addresses are guaranteed good nand C bad blocks cannot be used to store data endurance 100,000 with no cell failures 250,000 with some block failures nor C 100% of the array is guaranteed good after 100,00 cycles. nand C some additional failures can be expected. ai03446 2000 2001 2002 2003 2004 2005 0.1 1 silicon cost ($/mbyte) 2-bits/cell nor 2-bits/cell nand 4-bits/cell nor
AN1266 - application note 8/9 conclusion the difference in cell size between nor and nand flash memories will be compensated for when 4-bits per cell nor flash memories become available, turning nor technology into the most cost-effective stor- age solution for all applications. the other advantages of nor flash memories, such as being able to ex- ecute code directly from the flash memory, further enhance the cost-effectiveness of the technology. finally, flexible bus interfaces such as burst mode, page mode, and multiplexed buses make nor flash memories the easiest type of memory for all current and future applications. references [1] p. cappelletti, c. golla, p. olivo and e. zanoni, flash memories, kluwer academic publishers, 1999.
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